1. Field of the Invention
The present invention relates to clock synchronization of remotely distributed electronic devices, and more particularly, to accelerating the acquisition rate of a phase locked loop used in a timing recovery system
2. Background of the Invention
In the last several years distributed computing and communications systems that rely on or provide high speed data communications have become nearly ubiquitous. Such systems may include, but are not limited to, broadband communication systems using cable modems, satellite communication systems, fiber to the home (FTTH) communications networks, and board-to-board interconnections in a myriad of electronic devices.
In many of these systems, the clocks in remotely distributed devices must be synchronized for efficient operation. There are many reasons why remotely distributed devices may need to have their clocks synchronized. Two of the more common reasons relate to the efficient functioning of the devices. In particular, in a digital communication system the receiving device must be properly synched to a sending device to enable the efficient processing and interpretation of an incoming data stream. If the devices are not properly synchronized, the receiving device may not be able to properly interpret data being transmitted to it. Additionally, in a scenario where time division multiplexing is used to allocate bandwidth to many remotely distributed devices for signal transmission to a single master device, the remotely distributed devices often must be time synchronized. If the clocks of the remote devices are not synchronized with the clock of the master device, an undesirable situation may arise, such that, the remote devices transmit data at the same time or in the wrong time slots leading to confusion and loss of data at the master device.
Phase locked loop (PLL) systems are typically used to facilitate clock synchronization of remotely located devices. A PLL system is a feedback system in which the feedback signal is used to lock the output frequency and phase to the frequency and phase of an input signal. FIG. 1 illustrates the basic architecture of a PLL system. As depicted in FIG. 1 the basic components include phase detector 110, loop filter 120 and voltage controlled oscillator 130. Phase locked loops can be analog or digital with the majority being composed of both analog and digital components.
In the basic PLL system illustrated in FIG. 1, input signal V(t) 140 is applied to one input of phase detector 110 while the output signal X(t) 170 is applied to the other input of phase detector 110. The output of phase detector 110, E(t) 150, is a function of the phase difference between V(t) 140 and X(t) 170. Loop filter 120 filters out undesirable components from E(t) 150 and provides further control over the loop's frequency response. Thus, loop filter 120 produces an output signal, Y(t) 160, that is primarily a function of the phase difference between V(t) 140 and X(t) 170.
Voltage controlled oscillator 130 is an oscillator whose output frequency is a linear function of its input voltage over some range of input voltages. A positive voltage will cause the frequency of the output signal of voltage controlled oscillator 130 to be greater than its uncontrolled value, while a negative voltage will cause it to be less. When an input signal has a frequency and phase within a certain range, known as the capture range, the PLL system will go through a series of cycles in which the difference between V(t) 140 and X(t) 170 becomes smaller and smaller until the signals are substantially the same. The system is said to be “locked” when the frequency and the phase of V(t) 140 and X(t) 170 are substantially the same. If the input signal has a frequency and phase outside the capture range, the system will not achieve lock and V(t) 140 and X(t) 170 may diverge, instead of converging.
Acquisition rate is a key performance characteristic of a PLL system. Acquisition rate refers to the rate at which a PLL system achieves lock, that is, to generate an output signal, such as X(t) 170 that has the same phase and frequency as an input signal, such as V(t) 140. Acquisition rate is a function of a variety of factors. Among these factors are the quality of the circuit components, the range of the input signal frequency and phase, and the characteristics of the input signal (e.g., digital or analog, noise levels, etc.).
As communication speeds have increased, the need to accelerate acquisition rates has also increased. There are two basic situations when a PLL system needs to acquire lock to an input signal. These situations are upon system start-up and following the loss of lock during operation. When a PLL system is acquiring lock upon system start-up, the throughput degradation attributable to a slow acquisition rate may not be perceptible. However, when a system is operating and lock is lost, having a slow acquisition rate may significantly degrade performance. While start-up acquisition, by definition, only occurs once, re-acquisition during operation may occur many times. Because the re-acquisition occurs while data is likely being transmitted, data may be lost. The longer the re-acquisition, the more data is lost and the greater the time needed to recover the data. Thus, minimizing the acquisition time plays an important role in maximizing system throughput, particularly in environments where the signal or PLL lock may be lost frequently.
One type of communications system where the acquisition rate of clock signals is significant is a cable modem-based broadband communications system. Within a cable modem-based broadband communication system the two principle devices are cable modems and cable modem termination systems. In a broadband communications network that uses cable modems, typically many cable modems are connected to a single cable modem termination system. Cable modems are located at customer premises and typically connected to personal computers through an Ethernet connection. Cable modem termination systems are typically located within a service provider's network center, often known as a headend location. Cable modem termination systems exchange data with multiple cable modems at high speeds. Importantly, cable modem termination systems transmit clock signals to cable modems for synchronization that is critical to ensuring efficient operation and high throughput.
Cable modem networks transmit data at high speeds that require optimization of circuitry and procedures. In particular, in a typical cable modem network in the downstream direction (from the network to a user's computer) network speeds can reach 40 Mbps—an aggregate amount of bandwidth that is shared by multiple users. In some systems network speeds can reach speeds approaching 100 Mbs. Typically, the downstream speed per user is on the order of 1 to 3 Mbps. Thus, if acquisition of a clocking signal delays transmission of data by only a tenth of second, the cable modem termination system will be prevented from sending 4.0 Mb of data. Depending on how often clock synchronization is lost, this could result in a performance degradation of up to 10%. This is unlikely because clock synchronization is not typically lost once a second. Nonetheless, as service providers receive greater and greater pressure from consumers for higher speed transmission rates, it is critical for circuitry and procedures to be optimized.
Thus, when dealing with systems that are transmitting data at megabit speeds, such as current broadband cable modem communications systems, minimizing acquisition time is critical. While there currently are approaches to aid a PLL system to achieve lock and to reduce acquisition rates, these approaches are either relatively slow given current communication speeds or require complex circuitry.